1. Field of the Invention
The present invention relates to an improved spin system layout and control apparatus and methods for dispensing a process liquid onto a surface. More particularly, the present invention relates to improved spin coating system for the placement of photoresist and developer on a semiconductor substrate wafer.
2. Description of the Invention Background
Integrated circuits are typically constructed by depositing a series of individual layers of predetermined materials on a wafer shaped semiconductor substrate, or "wafer". The individual layers of the integrated circuit are in turn produced by a series of manufacturing steps. For example, in forming an individual circuit layer on a wafer containing a previously formed circuit layer, an oxide, such as silicon dioxide, is deposited over the previously formed circuit layer to provide an insulating layer for the circuit. A pattern for the next circuit layer is then formed on the wafer using a radiation alterable material, known as photoresist. Photoresist materials are generally composed of a mixture of organic resins, sensitizers and solvents. Sensitizers are compounds, such as diazonapthaquinones, that undergo a chemical change upon exposure to radiant energy, such as visible and ultraviolet light resulting in an irradiated material having differing salvation characteristics with respect to various solvents than the nonirradiated material. Resins are used to provide mechanical strength to the photoresist and the solvents serve to lower the viscosity of the photoresist so that it can be uniformly applied to the surface of the wafers. After a photoresist layer is applied to the wafer surface, the solvents are evaporated and the photoresist layer is hardened, usually by heat treating the wafer. The photoresist layer is then selectively irradiated by placing a radiation opaque mask containing a transparent portion defining the pattern for the next circuit layer over the photoresist layer and then exposing the photoresist layer to radiation. The photoresist layer is then exposed to a chemical, known as developer, in which either the irradiated or the nonirradiated photoresist is soluble and the photoresist is removed in the pattern defined by the mask, selectively exposing portions of the underlying insulating layer. The exposed portions of the insulating layer are then selectively removed using an etchant to expose corresponding sections of the underlying circuit layer. The photoresist must be resistant to the etchant, so as to limit the attack of the etchant to only the exposed portions of the insulating layer. Alternatively, the exposed underlying layer(s) may be implanted with ions which do not penetrate the photoresist layer thereby selectively penetrating only those portions of the underlying layer not covered by the photoresist. The remaining photoresist is then stripped using either a solvent, or a strong oxidizer in the form of a liquid or a gas in the plasma state. The next layer is then deposited and the process is repeated until fabrication of the semiconductor device is complete.
The handling and treatment of the wafers must take place in a clean room environment in order to prevent contamination of the layers. As a result, a significant portion of the cost involved with the photoresist processing stages are associated with the cost of maintaining the clean room. Therefore, a reduction in the overall production cost of the integrated circuit can be realized by reducing the amount of space, or "footprint", occupied by the equipment in the clean room. In addition, because all clean room activities must be shut down and an extensive cleanliness procedure followed after the performance of maintenance, further cost saving can be realized by minimizing the amount of maintenance time spent in the clean room.
Efforts in the prior art to date have focussed on minimizing floor space and increasing production capacity by integrating the resist processing system and automating the handling and treatment of the wafers using a centralized controller. One such system is disclosed in U.S. Pat. No. 4,985,722 issued to Ushijima et al. and related U.S. Pat. Nos. 5,177,514, 5,202,716 and 5,339,128. A problem that arises with the prior art integrated spin coating systems is that when the heating or cooling assemblies must be repaired or replaced, extensive and costly amounts of downtime occur because of the integration of the system. The costs are especially significant in a clean room environment in which all operations in he clean room have to be shut down until cleanliness can again be achieved at a cost of thousands of dollars an hour. Another problem that exists in the prior art is the amount of movement necessary by the wafer handling device which will tend to generate particulate contamination. In addition, because a path must be available for the movement of the wafer handler, this space is unavailable for other use and also will be unproductive during the portion of the process, in which the handling device is not located therein.
As such, the present invention is directed to modular process liquid dispense systems and methods using the same which overcome, among others, the above-discussed problems so as to provide a more easily controlled and maintained coating system having a smaller footprint for use in resist processing of semiconductor wafers.